1. Field of the Invention
The present invention relates to a method for forming a capacitor, and particularly to a method for forming a capacitor having a Metal-Insulator-Metal (MIM) structure in which metal or metal nitride films are employed as upper and lower electrodes.
2. Description of the Related Art
As DRAM components are fabricated with higher density processes, capacitors are also formed to be smaller in size. Accordingly, a dielectric material, having dielectric constant greater than that of SiO.sub.2, such as Al.sub.2 O.sub.3, TiO.sub.2, (Ba, Sr)TiO.sub.3, Pb(Zr, Ti)O.sub.3, is employed as capacitor dielectrics. In addition to the capacitor dielectrics having a high dielectric constant, upper and lower electrodes made of noble metal to reduce leakage current are provided to form a capacitor having a high dielectric constant.
First, explanation will be made of an example (referred to as a first conventional example) of a DRAM capacitor having a high dielectric constant with reference to FIGS. 1A, 1B and FIGS. 2A, 2B, highlighting a capacitor formation step and process steps just before and after the capacitor formation step.
In accordance with a process known to those skilled in the art, a silicon substrate 101, a field isolation film 102, gate oxide films 103, gate electrodes 104, LDD regions 105, diffusion layers 106, insulating films 107 formed on sidewalls of the gate electrodes 104, cobalt salicide layers 108, Si.sub.3N.sub.4 layers 109, interlayer dielectrics 110, connection holes 111, tungsten studs 113, etch stop layers 114, an interlayer silicon oxide layer 115 and openings 116 are formed (refer to FIG. 1A).
Subsequently, for example, a TiN film is deposited on the interlayer silicon oxide layer 115 using CVD or sputtering techniques. Then, the TiN film on the interlayer silicon oxide layer 115 is selectively etched back so that the TiN film is left only within each of the openings 116 to form lower electrodes 117 within the openings 116 (FIG. 1B). It should be noted that the etching back is performed by previously forming a resist film (not shown) within each of the openings 116 provided in the interlayer silicon oxide layer 115 in order to protect the lower electrode 117. The resist film is removed after completion of the etching back.
Subsequently, a TiO.sub.2 film is deposited as the capacitor dielectrics 119 using, for example, Atomic Layer Deposition (ALD) techniques (FIG. 2A). In this example, the two reactants are TiCl.sub.4 and H.sub.2 O. In this case, instead of H.sub.2 O, O.sub.3 may be used. The TiO.sub.2 film is deposited to a thickness of 10 to 30 nm. A deposition temperature employed is from 250.degree. to 400.degree. C. and pressure employed is from 25 mTorr to 1000 mTorr.
Thereafter, a lamination 122 of TiN and W layers (lower layer: TiN film 120, upper layer: W 121) is formed as an upper electrode using CVD, sputtering or ALD techniques (FIG. 2A). Then, the lamination 122 is, for example, dry etched in a desirable pattern that makes up an upper electrode 122 and thus a capacitor is formed (FIG. 2B).
FIG. 3A illustrates leakage characteristics of the capacitor formed as described above. As can be seen from the figure, leakage current greatly increases with voltage at any measurement temperature and grows greatly in high measurement temperature ranges, verifying that the capacitor of the first example cannot satisfy data retention requirements on DRAM.
Then, a second conventional example to improve leakage characteristics of the capacitor of the first conventional example will be explained below. In the second conventional example, process steps excluding the step of forming capacitor dielectrics film are approximately the same as those employed in the first conventional example and therefore, explanation thereof is omitted.
In accordance with the process similar to that employed in the first conventional example, components ranging starting from a MOSFET to a lower electrode are formed as shown in FIG. 1B.
Subsequently, an Al.sub.2 O.sub.3 film is formed as first capacitor dielectrics 218 using, for example, ALD techniques. The two reactants are Trimethyl Aluminum (TMA) and H.sub.2 O or O.sub.3. In this case, the Al.sub.2O.sub.3 film is deposited to a thickness of 1 to 5 nm. A deposition temperature employed is from 250.degree. to 400.degree. C. and pressure employed is from 25 mTorr to 1000 mTorr.
Thereafter, a TiO.sub.2 film is formed as second capacitor dielectrics 219 using, for example, ALD techniques (FIG. 4A) The two reactants are TiCl.sub.4 and H.sub.2 O. In this case, instead of H.sub.2 O, O.sub.3 may be used. The TiO.sub.2 film is deposited to a thickness of 1 to 15 nm. A deposition temperature employed is from 250.degree. to 400.degree. C. and pressure employed is from 25 mTorr to 1000 mTorr.
Thereafter, a lamination of TiN and W layers is formed as an upper electrode using, for example, CVD, sputtering or ALD techniques. Then, the lamination is, for example, dry etched in a desirable pattern that makes up an upper electrode 122 and thus a capacitor of the second conventional example is formed (FIG. 4B).
FIG. 3B illustrates leakage characteristics of the capacitor formed as described above. As can be seen from the figure, the capacitor of the second conventional example exhibits leakage characteristics which are greatly improved as compared to the capacitor of the first conventional example. However, instead, the capacitance per unit area is significantly reduced when compared with the capacitor of the first conventional example, as shown in FIG. 15.
In addition to the above-described capacitor dielectrics employed in the first and second conventional examples, another capacitor dielectrics, having low leakage current, such as a lamination of ZrO.sub.2, TiO.sub.2 and ZrO.sub.2 layers or a lamination of HfO.sub.2, TiO.sub.2 and HfO.sub.2 layers is disclosed in Japanese Patent Application No. 5(1993)-13706. Furthermore, Japanese Patent Application No. 2002-222934 to the inventors of the application discloses alternative capacitor dielectrics having low dependence of leakage current on temperatures and employing an Al.sub.2 O. sub.3 film as a barrier insulating layer.
However, the capacitor dielectrics employed in the first and second conventional examples cannot satisfy the requirements that a DRAM capacitor has a high capacitance and at the same time, allows leakage current flowing there though to be maintained at a low level. Although Japanese Patent Application No. 5(1993)-13706 teaches that the capacitance insulating film employed therein is so effective to obtain high capacitance and low leakage current, it never gives detailed description of how leakage current through the capacitor dielectrics vary with temperatures and of what types of capacitor formation methods are employed to reduce the leakage current. During operation of semiconductor device, it must be ensured that a semiconductor device operates at a temperature of up to about 150.degree. C. and particularly, a semiconductor device fabricated incorporating together a memory device and a logic device is strongly required to allow leakage current flowing through capacitors used in the semiconductor device to be maintained at a low level even at high operating temperatures. Moreover, as described above, the technique disclosed in Japanese Patent Application No. 2002-222934 does not provide a method for forming a capacitor with a high capacitance because the capacitor incorporates therein an Al.sub.2 O.sub.3 film as a barrier insulating layer.